EMTime/libopencm3-examples
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Updated libopencm3 to current master. Made all examples compile again.

Browse Source 
Be specifically careful with the usb examples. There is likely some
breakage to be expected, not sure I updated all the drivers to the
correct types for the respective chips.
This commit is contained in:
Piotr Esden-Tempski
2015-12-15 00:56:25 +01:00
parent f0009c64dc
commit 976720c355
48 changed files with 58 additions and 58 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
examples/stm32/l1/stm32l-discovery/button-irq-printf-lowpower/main.c
View File

@@ -148,8 +148,8 @@ static int setup_rtc(void)
RCC_CSR &= ~RCC_CSR_RTCRST;
/* We want to use the LSE fitted on the discovery board */
rcc_osc_on(LSE);
rcc_wait_for_osc_ready(LSE);
rcc_osc_on(RCC_LSE);
rcc_wait_for_osc_ready(RCC_LSE);
/* Select the LSE as rtc clock */
rcc_rtc_select_clock(RCC_CSR_RTCSEL_LSE);
@@ -260,11 +260,11 @@ static int process_state(volatile struct state_t *st)
static void reset_clocks(void)
{
/* 4MHz MSI raw range 2*/
clock_scale_t myclock_config = {
struct rcc_clock_scale myclock_config = {
.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.voltage_scale = RANGE2,
.voltage_scale = PWR_SCALE2,
.flash_config = FLASH_ACR_LATENCY_0WS,
.apb1_frequency = 4194000,
.apb2_frequency = 4194000,

2
examples/stm32/l1/stm32l-discovery/button-irq-printf/main.c
View File

@@ -35,7 +35,7 @@ int _write(int file, char *ptr, int len);
static void clock_setup(void)
{
rcc_clock_setup_pll(&clock_config[CLOCK_VRANGE1_HSI_PLL_24MHZ]);
rcc_clock_setup_pll(&rcc_clock_config[RCC_CLOCK_VRANGE1_HSI_PLL_24MHZ]);
/* Lots of things on all ports... */
rcc_periph_clock_enable(RCC_GPIOA);
rcc_periph_clock_enable(RCC_GPIOB);

14
examples/stm32/l1/stm32l-discovery/lcd-display/lcd-hello.c
View File

@@ -49,15 +49,15 @@ static void lcd_init(void)
rcc_periph_clock_enable(RCC_PWR);
rcc_periph_clock_enable(RCC_LCD);
pwr_disable_backup_domain_write_protect ();
rcc_osc_on (LSE);
rcc_wait_for_osc_ready (LSE);
rcc_rtc_select_clock (RCC_CSR_RTCSEL_LSE);
rcc_osc_on(RCC_LSE);
rcc_wait_for_osc_ready(RCC_LSE);
rcc_rtc_select_clock(RCC_CSR_RTCSEL_LSE);
RCC_CSR |= RCC_CSR_RTCEN; /* Enable RTC clock */
pwr_enable_backup_domain_write_protect ();
/* Map SEG[43:40] to SEG[31:28], use 4 LCD commons, use 3 voltage levels
when driving LCD display */
lcd_enable_segment_multiplexing ();
lcd_enable_segment_multiplexing();
lcd_set_duty (LCD_CR_DUTY_1_4);
lcd_set_bias (LCD_CR_BIAS_1_3);
@@ -66,9 +66,9 @@ static void lcd_init(void)
/* And increase contrast */
lcd_set_contrast (LCD_FCR_CC_5);
lcd_enable ();
do {} while (!lcd_is_enabled ());
do {} while (!lcd_is_step_up_ready ());
lcd_enable();
do {} while (!lcd_is_enabled());
do {} while (!lcd_is_step_up_ready());
}
static void clear_lcd_ram(void)