EMTime/libopencm3-examples
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timer_reset -> rcc_periph_reset_pulse() replace

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timer_reset wasn't fully implemented for all timers on all series, and
was simply a wrapper of the RST bits in the RCC registers anyway.

First part of https://github.com/libopencm3/libopencm3/issues/709
This commit is contained in:
Karl Palsson
2016-12-14 15:15:17 +00:00
committed by Karl Palsson
parent 833da68c18
commit 1260b16772
11 changed files with 12 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
examples/stm32/f1/lisa-m-2/adc_injec_timtrig/adc_injec_timtrig.c
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@@ -70,7 +70,7 @@ static void timer_setup(void)
rcc_periph_clock_enable(RCC_TIM2);
/* Time Base configuration */
timer_reset(timer);
rcc_periph_reset_pulse(RST_TIM2);
timer_set_mode(timer, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_period(timer, 0xFF);

2
examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq/adc_injec_timtrig_irq.c
View File

@@ -73,7 +73,7 @@ static void timer_setup(void)
rcc_periph_clock_enable(RCC_TIM2);
/* Time Base configuration */
timer_reset(timer);
rcc_periph_reset_pulse(RST_TIM2);
timer_set_mode(timer, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_period(timer, 0xFF);

2
examples/stm32/f1/lisa-m-2/adc_injec_timtrig_irq_4ch/adc_injec_timtrig_irq_4ch.c
View File

@@ -81,7 +81,7 @@ static void timer_setup(void)
rcc_periph_clock_enable(RCC_TIM2);
/* Time Base configuration */
timer_reset(timer);
rcc_periph_reset_pulse(RST_TIM2);
timer_set_mode(timer, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
timer_set_period(timer, 0xFF);

2
examples/stm32/f1/stm32-h103/pwm_6step/pwm_6step.c
View File

@@ -110,7 +110,7 @@ static void tim_setup(void)
nvic_enable_irq(NVIC_TIM1_TRG_COM_IRQ);
/* Reset TIM1 peripheral. */
timer_reset(TIM1);
rcc_periph_reset_pulse(RST_TIM1);
/* Timer global mode:
* - No divider

2
examples/stm32/f1/stm32-h103/timer/timer.c
View File

@@ -77,7 +77,7 @@ static void tim_setup(void)
nvic_enable_irq(NVIC_TIM2_IRQ);
/* Reset TIM2 peripheral. */
timer_reset(TIM2);
rcc_periph_reset_pulse(RST_TIM2);
/* Timer global mode:
* - No divider